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From: kds@blabla.intel.com (Ken Shoemaker)
Newsgroups: comp.arch
Subject: Re: Load/Branch ratio [was Re: 486 and 68040]
Message-ID: <4006@mipos3.intel.com>
Date: 1 May 89 20:26:44 GMT
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Reply-To: kds@blabla.UUCP (Ken Shoemaker)
Organization: Santa Clara Microprocessor Division, Intel Corp., Santa Clara, CA
Lines: 32

With X86 code we have looked at, about 1 in 3 instructions does a memory
load, 1 in 6 does a memory write, and 1 in 6 is a branch.  Note that this
may not be the same as many risc machines because:

	1) we have fewer registers, thus more of the context is in memory
	2) we can use memory locations directly as operands in operations

As John said, you need to look at the problem you are solving before you can
solve it.  Using some else's solution may not be appropriate because they
may not have the same problem!

In the i486, a prefetch will never "bounce" a memory access: there is 1 clock
throughput for all memory targeting instructions.  We know enough in advance
when a memory read or write is going to occur that we can keep any prefetch
requests out of the way.  Any stalls that would occur with respect to reads
should only happen in relation to cache misses.

This isn't really new: the 386 does a similar thing.  Only there is a 2
clock throughput for memory targeting instructions on the 386 because all
references to external memory take at least two clocks.  But in this case,
too, we will stop any prefetch/instruction access bus cycle if they would
remain on the bus beyond when we are ready to send the read/write addresses.
This is true only for a zero wait state bus, however.  But it is one way
that the i486 is simpler than the 386.

And I lied.  The i486 article in Microprocessor Report won't be coming out
until the June issue.  The May issue will describe the i486 bus.
-----------
I've decided to take George Bush's advice and watch his press conferences
	with the sound turned down...			-- Ian Shoales
Ken Shoemaker, Microprocessor Design, Intel Corp., Santa Clara, California
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