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From: keith@mips.COM (Keith Garrett)
Newsgroups: comp.arch
Subject: ESD protection (was Re: Do you have bandwidth?)
Keywords: protection static ESD
Message-ID: <18682@gumby.mips.COM>
Date: 2 May 89 20:29:39 GMT
References: <407@bnr-fos.UUCP> <7766@thorin.cs.unc.edu> <418@bnr-fos.UUCP> <6658@cbmvax.UUCP> <396@dalcsug.UUCP>
Reply-To: keith@mips.COM (Keith Garrett)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 21

In article <396@dalcsug.UUCP> erskine@dalcsug.UUCP (Neil Erskine) writes:
>In article <6658@cbmvax.UUCP> jesup@cbmvax.UUCP (Randell Jesup) writes:
>>[bandwidth limited by capacitive loading due to static protection and fan-out]
>
>	I'm no engineer, but if the capacitive pad loads are
>restricting the speed of off-chip signalling, why not dispense with
>them, and provide the static protection at the board level?  This
>might make board assembly more costly (due to the increased care
>required), and the board itself more costly (it might have to be
>encased in metal), but if it gives a significant degree of additional
>speed, the bother and expense seem worth it.  Alternatively, there may
>be some reasons why board level protection can't do the job; in which
>case what are those reasons?

ESD (static) protection is required to protect the ic's during handling before
they are place on boards. the need increases with the smaller devices used in
advanced technologies.
-- 
Keith Garrett        "This is *MY* opinion, OBVIOUSLY"
UUCP: keith@mips.com  or  {ames,decwrl,prls}!mips!keith
USPS: Mips Computer Systems,930 Arques Ave,Sunnyvale,Ca. 94086