Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ncar!ames!lll-winken!uunet!wucs1!jps
From: jps@wucs1.wustl.edu (James Sterbenz)
Newsgroups: comp.arch
Subject: Re: Do you have bandwidth?
Keywords: memory bandwidth latency
Message-ID: <833@wucs1.wustl.edu>
Date: 2 May 89 16:27:10 GMT
References: <407@bnr-fos.UUCP> <7766@thorin.cs.unc.edu> <23649@agate.BERKELEY.EDU>
Reply-To: jps@wucs1.UUCP (James Sterbenz)
Organization: Washington University, St. Louis, MO
Lines: 30

In article <23649@agate.BERKELEY.EDU> matloff@heather.ucdavis.edu (Norm Matloff) writes:

>These measures, e.g. wider buses, may just shift the bottleneck to 
>something else.  There is still a strong limitation on a chip's 
>number of pins, right?  The area of a rectangle grows much faster 
>than the perimeter, and of course there are mechanical reasons why 
>pins can't be too small.

This is a problem with packages that have pins only on the perimeter
(such as DIPs), but not for PGAs.  Of course, pin limitation is still
a problem, but not quite as bad for PGAs.

>Thus the ratio of number of I/O channels
>of a chip to bits stored in the chip will probably get worse, not
>better.

In spite of all the other things that most of us think as important,
packaging remains one of the most important limitations to system
performance.  This is one of the reasons that micros and workstations
will have trouble reaching the performance of mainframes and supercomputers;
current high performance packaging and cooling is just too expensive.

It will be very interesting to see what happens when a cheap, easy
chip interconect allowing close 3-D stacking becomes available
(assuming corresponding cooling).
-- 
James Sterbenz  Computer and Communications Research Center
                Washington University in St. Louis 314-726-4203
INTERNET:       jps@wucs1.wustl.edu
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