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From: tim@crackle.amd.com (Tim Olson)
Newsgroups: comp.arch
Subject: Re: Bandwidth and RISC vs. CISC
Message-ID: <25504@amdcad.AMD.COM>
Date: 3 May 89 15:38:33 GMT
References: <38853@bbn.COM> <423@bnr-fos.UUCP> <288@ctycal.UUCP> <1262@l.cc.purdue.edu> <231@celit.UUCP> <10544@cit-vax.Caltech.Edu>
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In article <10544@cit-vax.Caltech.Edu> yair@tybalt.caltech.edu.UUCP (Yair Zadik) writes:
| A couple of years ago there was an article in Byte about a proposed design
| which they called WISC for Writeable Instruction Set Computer.  The idea
| was to do a RISC or microcoded processor which had an on board memory 
| containing macros which behaved like normal instructions (I guess it was
| on EEPROM like memory).  That way, each compiler could optimize the 
| instruction set for its language.  The end result (theoreticly) is that
| you get the efficiency of RISC with the memory bandwith of CISC.  I haven't
| heard else about it.  Is anyone out there working on such a processor or is
| it just a bad idea?

"WISC" is just a new term for how most people build microcoded machines
(SRAMs are faster than EPROMS/ROMS).  I don't see how you can get "the
efficiency of RISC with the memory bandwidth of CISC" using such a
design.

The way CISCs attempt to reduce memory bandwith is to make an
instruction do as much as possible, so fewer are needed to perform an
operation.  This is the antithesis of RISC, which, by using simple
"building-block" instructions, allows the compiler to perform many more
optimizations.

The way to reduce memory bandwith while maintaining performance is to
change the Writeable Control Store into an instruction cache.


	-- Tim Olson
	Advanced Micro Devices
	(tim@amd.com)