Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!bbn!rochester!pt.cs.cmu.edu!fas.ri.cmu.edu!schmitz
From: schmitz@fas.ri.cmu.edu (Donald Schmitz)
Newsgroups: comp.arch
Subject: Re: Do you have bandwidth?
Keywords: memory bandwidth latency
Message-ID: <4883@pt.cs.cmu.edu>
Date: 3 May 89 14:10:48 GMT
Distribution: na
Organization: Carnegie-Mellon University, CS/RI
Lines: 18
References:

>In spite of all the other things that most of us think as important,
>packaging remains one of the most important limitations to system
>performance.  This is one of the reasons that micros and workstations
>will have trouble reaching the performance of mainframes and supercomputers;
>current high performance packaging and cooling is just too expensive.

Just saw a blurb in one of the trade papers about a new inter-connect
technology, developed by Cinch, called "Cinapse".  I'm still waiting on info,
but from the description, they use silver butt contacts - I'm guessing the
trick is to somehow make the contacts be springy to make sure all of them in
an array touch.  From memory, the density was about twice that of current
PGAs (240 contacts/in^2 sticks in my mind).  They are pushing this as a bus
connector technology, but it seems possible to use it for chips too.

Interesting question, if packaging allowed you to have twice as many pins per
CPU (pick your favorite existing design), what would you do with them?

Don Schmitz
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