Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!unmvax!polyslo!cquenel From: cquenel@polyslo.CalPoly.EDU (24 more school days) Newsgroups: comp.arch Subject: Re: Bandwidth and RISC vs. CISC Keywords: WISC, writable instruction store Message-ID: <10981@polyslo.CalPoly.EDU> Date: 3 May 89 19:34:03 GMT References: <38853@bbn.COM> <423@bnr-fos.UUCP> <288@ctycal.UUCP> <1262@l.cc.purdue.edu> <231@celit.UUCP> <10544@cit-vax.Caltech.Edu> <1827@ccncsu.ColoState.EDU> Reply-To: cquenel@polyslo.CalPoly.EDU (24 more school days) Organization: Blue Blaze Irregulars Lines: 26 In article <10544@cit-vax.Caltech.Edu> (Yair Zadik) writes: |WISC for Writeable Instruction Set Computer. The idea ... In article <1827@ccncsu.ColoState.EDU> (Jon Buller) writes: | The only problem with this is that doing a context switch is nearly | impossible. Imagine not only saving registers but having to swap | out microcode and instructions too. ... In 9690 ted@nmsu.edu (Ted Dunning) sez: |isn't this leading right back to a normal risc with a cache that |allows programs to share executable segments? Actually, no. The point is that micro-code is much more static over the life of a process. A seperate cache of already-broken-down, easy to execute micro-code would be carrying RISC to an extreme (simple instructions), but would get around the icache/bandwidth problem inherent in conventional RISCs. -- @---@ ----------------------------------------------------------------- @---@ \. ./ | Chris (The Lab Rat) Quenelle cquenel@polyslo.calpoly.edu | \. ./ \ / | You can keep my things, they've come to take me home -- PG | \ / ==o== ----------------------------------------------------------------- ==o==