Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!lll-lcc!pyramid!cbmvax!jesup
From: jesup@cbmvax.UUCP (Randell Jesup)
Newsgroups: comp.arch
Subject: Re: Do you have bandwidth?
Keywords: memory bandwidth latency
Message-ID: <6759@cbmvax.UUCP>
Date: 3 May 89 19:36:55 GMT
References: <407@bnr-fos.UUCP> <7766@thorin.cs.unc.edu> <23649@agate.BERKELEY.EDU> <833@wucs1.wustl.edu>
Reply-To: jesup@cbmvax.UUCP (Randell Jesup)
Organization: Commodore Technology, West Chester, PA
Lines: 12

In article <833@wucs1.wustl.edu> jps@wucs1.UUCP (James Sterbenz) writes:
>This is a problem with packages that have pins only on the perimeter
>(such as DIPs), but not for PGAs.  Of course, pin limitation is still
>a problem, but not quite as bad for PGAs.

	But then again PGA's have thermal expansion coefficient problems due
to mismatch with the coefficient of board they mount on (or so I was told).
That's why the RPM-40 in in a leadless chip carrier instead of a PGA.  (Perhaps
PGA's with sufficient pins weren't rated for 40 MHz, either.)

-- 
Randell Jesup, Commodore Engineering {uunet|rutgers|allegra}!cbmvax!jesup