Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!cs.utexas.edu!uunet!portal!cup.portal.com!bcase From: bcase@cup.portal.com (Brian bcase Case) Newsgroups: comp.arch Subject: Re: Bandwidth and RISC vs. CISCOM Message-ID: <17932@cup.portal.com> Date: 4 May 89 17:15:02 GMT References: <38853@bbn.COM> <423@bnr-fos.UUCP> <288@ctycal.UUCP> <1262@l.cc.purdue.edu> <231@celit.UUCP> <10544@cit-vax.Caltech.Edu> <102714@sun.Eng.Sun.COM> Organization: The Portal System (TM) Lines: 33 >>A couple of years ago there was an article in Byte about a proposed design >>which they called WISC for Writeable Instruction Set Computer. >Honeywell and Buro..whoops UNISYS had mainframes like this, well over >a decade ago. Byte, lives at the cutting edge.... Yes. Such a machine was (is) referred to as a "soft machine." Reading Byte can be hazardous to your health.... The original complaint that "RISC machines use too much memory bandwidth" is where the problem with the whole argument lies. The correct assertion is that "high-performance machines use too much memory bandwidth." That is, RISC or CISC has little to do with it. A high-performance machine will have a good optimizing compiler and its peak instruction rate will be close to, if not at, the clock rate. The compiler will use the simple instructions because that is the best way to cut out cycles. Thus, memory bandwidth is mostly a function of the performance of the system. Soft machine or "WISC" is a bad idea because a truly horizontal microarchitecture is not amenable (enough) to automatic instruction-set customization. Going to a vertical microarchitecture to make the job tractible is called RISC. If the problem of generating horizontal micro- code can be solved, then the best use of it is not soft machines (WISC), but the same a old thing: make the horizontal set *the* instruction set and make the compiler generate code for it directly. The instruction cache will then capture the dynamic behavior of the program. Note that VLIWs and the i860 in dual-instruction mode are like horizontal machines. These architectures will eventually force advanced compilation techniques into the mainstream (years from now), and machine architectures in general might get more horizontal. Or maybe superscalar architectures will take over (note that superscalar both hides and exposes the horizontal microarchitecture at the same time: it will run old, vertical code just fine, but if you arrange things right, you'll get more "horizontalization.").