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From: bcase@cup.portal.com (Brian bcase Case)
Newsgroups: comp.arch
Subject: Re: WISC (Bandwidth and RISC vs. CISC)
Message-ID: <17933@cup.portal.com>
Date: 4 May 89 17:33:35 GMT
References: <38853@bbn.COM> <423@bnr-fos.UUCP> <288@ctycal.UUCP> <1262@l.cc.purdue.edu> <231@celit.UUCP> <10544@cit-vax.Caltech.Edu> <10978@polyslo.CalPoly.EDU>
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>Well, what do people think [about WISC]?

>I know it's a lot of trouble, but you could relieve a lot of the pressure
>that RISC puts on the icache (and consequently the memory bus).

Oh, OH, OH MY GOD, my instruction cache is about to BLOW UP from all that
pressure!!  It's gonna blow!  RUN FOR YOUR LIVES!!  [Oh come on, it's just
a joke.  I'm not flaming.]

The point I want to make is that if RISC (or anything else) keeps the 
instruction cache 100% busy, THAT IS GOOD, NOT BAD.  This means that the
trouble spent building the damn thing was really worth it, to say it one
way.  This is not "pressure."  The fact is that instruction caches work
really well.  There is no need to "help them out" or "relieve a lot of
the pressure put on them."  People seem to think that cache designs and
bus designs are right at the breaking point.  We're just lucky that we
were able to build satisfactory caches and buses for this generation of
machines, but, "Oh m'God, what about the next generation?  There's just
nothing left, we've run out of trickery!"  This is not true.  Cache and
bus designs are right at the edge of what is needed for a particular
generation of machines *BY DESIGN*.  To build something radically beyond
what is needed is a waste of money, and designers know it.  Sure, this
is hard stuff at 50 MHz and beyond.  But to think that we need to
go back to CISC or soft machines as a solution is probably not right.
To me, arguing for CISC in the face of high-frequency implementation
problems is equivalent to saying:  "These machines is runnin' too fast;
what say let's slow 'em down agin."

David Letterman:  "We are very near the end of civilization."