Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!leah!rpi!batcomputer!cornell!rochester!pt.cs.cmu.edu!MATHOM.GANDALF.CS.CMU.EDU!lindsay
From: lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay)
Newsgroups: comp.arch
Subject: Re: Do you have bandwidth?
Keywords: memory bandwidth latency
Message-ID: <4915@pt.cs.cmu.edu>
Date: 5 May 89 22:43:11 GMT
References: <407@bnr-fos.UUCP> <7766@thorin.cs.unc.edu> <23649@agate.BERKELEY.EDU> <833@wucs1.wustl.edu> <6759@cbmvax.UUCP> <18753@obiwan.mips.COM>
Organization: Carnegie-Mellon University, CS/RI
Lines: 20

In article <18753@obiwan.mips.COM> mark@mips.COM (Mark G. Johnson) writes:
>Hewlett-Packard's most recent HP-n000 series microprocessor, built in
>NMOS, dissipates 26 Watts and is mounted in a 408 pin PGA.

That's an impressive number of pins. It's probably not very dense,
though - on 100-mil centres, that's over four square inches, to hold
a square centimeter (or so) of chip.  Long paths!  Also, pins take up
board area, since they go through all signal layers, rather than just
through relevant ones.

One obvious improvement is to go surface mount, with a pad-grid
array.  The Motorola "Hypermodule" uses 88000's mounted in these.
I've only seen photos so far, but the claim is 288 pads in 1.1 inch x
1.1 inch, using 60-mil centres.

Actually, there's only 143 signal lines - the rest are power, ground,
and thermal. It will be interesting to see the response from
competitors.
-- 
Don		D.C.Lindsay 	Carnegie Mellon School of Computer Science
--