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From: dean@mars.Berkeley.EDU (R. Drew Dean)
Newsgroups: comp.arch
Subject: Re: SISC
Message-ID: <13359@pasteur.Berkeley.EDU>
Date: 6 May 89 02:29:50 GMT
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Reply-To: dean@xcssun.Berkeley.EDU (R. Drew Dean)
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While this subject started out as a joke, I point the net back to the
discussion a few months ago about a _real_ one instruction CPU:
Subtract & Branch Negative.  The instruction looks like
	SUBN source1, source2, next
source1 <- source1 - source2; if(source1 < 0) PC <- next else PC <- PC + 12;
Others have shown that this is Turing equivalent.  It would seem that generating
optimal code for this machine would be easy -- just generate the shortest
sequence of instructions possible -- all (1) instruction(s) take the same
amount of time, (I'd hope you'd pipeline it (easy) to get it down to 1 CPI),
so the code generator doesn't have to worry about much.

Of course, to really make this thing scream, it needs to run at about 300 MHz,
and have a _lot_ of 3 ns memory...:-)  You might want to try microcoding a
RISCy instruction set on it, but it would be memory-memory, as the chip
has no registers other than the PC.

I remember someone (sorry, I forget who) on the net saying that they had
started to write a Pascal compiler for this beast....


Drew Dean
Internet: dean@xcssun.berkeley.edu
UUCP: ...!ucbvax!xcssun!dean
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