Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!lll-winken!uunet!dg!rec
From: rec@dg.dg.com (Robert Cousins)
Newsgroups: comp.arch
Subject: Re: Criteria for comparing RISC processors
Message-ID: <163@dg.dg.com>
Date: 5 May 89 14:13:18 GMT
References: <2368@ogccse.ogc.edu> <1464@cfa.cfa.harvard.EDU> <141@dg.dg.com> <18120@winchester.mips.COM> <144@dg.dg.com> <18316@winchester.mips.COM> <147@dg.dg.com> <18653@winchester.mips.COM> <102441@sun.Eng.Sun.COM> <157@dg.dg.com> <24953@ames.arc.nasa.gov>
Reply-To: rec@dg.UUCP (Robert Cousins)
Organization: Data General, Westboro, MA.
Lines: 54

In article <24953@ames.arc.nasa.gov> lamaster@ames.arc.nasa.gov (Hugh LaMaster) writes:
>In article <157@dg.dg.com> rec@dg.UUCP (Robert Cousins) writes:
>>Your point is well taken.  By saying "Mhz for Mhz," I was attempting to make
>>sure that reasonable machines are being compared.  There is a penchant in
>>Dollar for dollar comparisons don't apply when there is no overlap
>Dollar for dollar comparisons are really the result of, not the input to,
>the architectural question.  

I disagree.  If one plans to build a high end product, the architecture
can include more features.  If one plans a low end product, the features
must be more utilitarian and priority based.  We wanted to deliver a product
with high-end CPU power at low end prices.  This means that we were forced
to carefully scrutinize each feature and component to get the maximum
bang per buck.  

>It depends too much on financial and marketing
>considerations of the companies involved.  Know any companies which have
>deliberately held back technology to avoid affecting current products?

I can name one which hasn't done it with its latest 88K workstation. . . .

>>High end to high end suffers from the same problem:  one person's high
>Actually, with a given technology this isn't too bad.  If you know that the
>technology is the high end, that is, and not affected by marketing, as above
>>Low end to low end is somewhat more fair.  In this space, the design
>>$/MIP is the most fair since it more readily allows people to judge
>Marketing affects this too much again...

Marketing has a limited ability to influence these ratios.  However, there
are very few workstations which are able to ship for $500/MIPS.  There aren't
even any close which I am aware of.  Sure marketing may be able to sway the
pricing by 10% either way, but not 50% or 100%.  What this whole thing boils
down to is the quality of the underlying technology and its architectural
implementation.

>If you want to get into implementation issues, are there architectural reasons
>why EVERYBODY can't do f.p. adds in two cycles?

While this is a reasonable question (and suitable for further discussion
here), there is a more basic question:  What architectures enforce a given
latency upon their instructions.  Some RISC processors work without interlocks
or scoreboarding so that the compilers are required to keep track of instructionlatency.  This means that if the instruction latency changes, all software
must be recompiled!  (Sounds like the stone ages to me.)

>  Hugh LaMaster, m/s 233-9,  UUCP ames!lamaster
>  NASA Ames Research Center  ARPA lamaster@ames.arc.nasa.gov
>  Moffett Field, CA 94035     
>  Phone:  (415)694-6117       

Robert Cousins
Dept. Mgr, Workstation Dev't.
Data General Corp.

Speaking for myself alone.