Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!lll-winken!uunet!dg!mpogue
From: mpogue@dg.dg.com (Mike Pogue)
Newsgroups: comp.arch
Subject: Re: Criteria for comparing RISC processors
Message-ID: <164@dg.dg.com>
Date: 5 May 89 14:30:38 GMT
References: <2368@ogccse.ogc.edu> <1464@cfa.cfa.harvard.EDU> <141@dg.dg.com> <18120@winchester.mips.COM> <144@dg.dg.com> <18316@winchester.mips.COM> <147@dg.dg.com> <18653@winchester.mips.COM> <102441@sun.Eng.Sun.COM> <156@dg.dg.com> <102927@sun.Eng.Sun.COM>
Reply-To: uunet!dg!mpogue (Mike Pogue)
Organization: Data General, Westboro, MA.
Lines: 39

In article <102927@sun.Eng.Sun.COM> khb@sun.UUCP (Keith Bierman - SPD Languages Marketing -- MTS) writes:
>maybe, maybe not. If Prisma meets their schedules you will be proved
>wrong around Jan 1990.
>

  My point is that a GaAs implementation cannot be compared ARCHITECTURALLY 
against a CMOS implementation.

  We are comparing architectures here, and the MIPS, 88K, and SPARC
architectures are all pretty similar, given the same technology
(implementation).

  We are, as has been announced, working on high speed ECL implementations
of the 88K, and it would probably be wise to assume that a GaAs 
implementation is being worked on somewhere, too (its probably wise to 
assume that EVERYONE is working on GaAs).

  You can't compare a CMOS anything against a GaAs anything, and expect
to make sense.  Its apples and oranges!

  Let's look at architecture, folks, not implementation!  Each architecture
has its pluses and minuses, but the facts show that they are all pretty
much the same on the major points:

    Heavily pipelined
    Large number of registers
    Smart Compilers

  On the lesser (but still important) points:

    Multiprocessor support (88K wins)
    Register scoreboarding (88K wins)
    Register Windows (debatable whether this is a win for SPARC or not)
    DM Cache (MIPS wins on performance, but not on price)

Mike Pogue
Data General Corp

My opinions are my own....