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From: kds@blabla.intel.com (Ken Shoemaker)
Newsgroups: comp.arch
Subject: Re: WISC (Bandwidth and RISC vs. CISC)
Message-ID: <4040@mipos3.intel.com>
Date: 5 May 89 20:56:23 GMT
References: <38853@bbn.COM> <423@bnr-fos.UUCP> <288@ctycal.UUCP> <1262@l.cc.purdue.edu> <231@celit.UUCP> <10544@cit-vax.Caltech.Edu> <10978@polyslo.CalPoly.EDU> <17933@cup.portal.com>
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Reply-To: kds@blabla.UUCP (Ken Shoemaker)
Organization: Santa Clara Microprocessor Division, Intel Corp., Santa Clara, CA
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I think the problem isn't one to get solved by downloadable microcode.  As
discussed previously, this is really almost the as just having a risc with a
good high speed instruction cache.  Complex instructions implemented just a
branches into the high speed downloadable cache don't really go any faster.

However, if you have complex instructions, then this really is low hanging
fruit in terms of superscaler implementations because a single instruction
specifies multiple things to do.  If you can do all these things in a single
clock, voila.  However, solving this problem requires adding more functional
blocks, e.g., adders, address paths, register ports, etc. to the 
implementation.
------------
I've decided to take George Bush's advice and watch his press conferences
	with the sound turned down...			-- Ian Shoales
Ken Shoemaker, Microprocessor Design, Intel Corp., Santa Clara, California
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