Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!lll-winken!maddog.llnl.gov!brooks
From: brooks@maddog.llnl.gov
Newsgroups: comp.arch
Subject: Register Scoreboarding
Message-ID: <24821@lll-winken.LLNL.GOV>
Date: 7 May 89 07:47:17 GMT
Sender: usenet@lll-winken.LLNL.GOV
Reply-To: brooks@maddog.llnl.gov ()
Organization: Lawrence Livermore National Laboratory
Lines: 17


A fellow from SUN has asked "What is so magic about register scoreboarding?"

Register scoreboarding allow you to change the pipeline delays of the
functional units in the processor, and tolerate stochastic pipeline
delays for memory, without any hassles.  A consequence of this, for
the Cray line, is that the same binaries can be run on the Cray-1,
Cray-XMP, Cray-YMP series.  The pipeline delays are different for these
three machines.  On all of these machines accesses to main memory are
fully pipelined, and to not stall the processor on a "cache miss" as is
common for their little microchip brethren.  Pipelining cache misses,
providing full memory bandwidth which can keep the functional units of the
processors fed, is a trick that the micros have yet to exploit.  Register
scoreboarding is again part of this game because memory latency is
stochastic.

brooks@maddog.llnl.gov, brooks@maddog.uucp