Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!lll-winken!uunet!mcvax!ukc!dcl-cs!aber-cs!pcg
From: pcg@aber-cs.UUCP (Piercarlo Grandi)
Newsgroups: comp.arch
Subject: Re: WISC "impossibility"
Summary: B1700/B1800 was a WISC. And Pretty Good.
Message-ID: <909@aber-cs.UUCP>
Date: 6 May 89 19:58:19 GMT
Reply-To: pcg@cs.aber.ac.uk (Piercarlo Grandi)
Distribution: eunet,world
Organization: Dept of CS, UCW Aberystwyth
	(Disclaimer: my statements are purely personal)
Lines: 33

In article <1140@ptolemy.arc.nasa.gov> raymond@ptolemy.arc.nasa.gov.UUCP (Eric A. Raymond) writes:
    >A couple of years ago there was an article in Byte about a proposed design
    >which they called WISC for Writeable Instruction Set Computer.  The idea
    
    Am I missing something?  Wouldn't a machine with loadable microcode
    satisfy this?  Hasn't that been done for years (and was was the floppy
    disk was designed to store)?  Even LISPM's have it.

Uh. You are right. It is time to mention the Burroughs B1700/B1800, about
which the late Organick wrote a very interesting book. It had as many
microcodes/instruction sets as needed. The B1800 could even page it. Code
density was impressive, and so was speed, considering the technology. It
had also some funny details (bit addressing!).

In a sense the ultimate CISC. It does support the RISC's advocates
contention that a (single) CISC machine special instructions are not
general enough, so why bother.

I agree, by the way, with Spencer's earlier remark about RISC+fast quick
bytecode interpreter == WISC. In particular, look at the TRANSPUTER:
its has 2k fast on chip RAM. What for? :->

As to me, my favourite machine architecture (the ultimate RISC?) would be a
Burroughs zero address mainframe (8 bit instructions, no registers) but with
four stacks (to avoid multiplexing a single stack top, and giving an effect
similar to multiple scratch register optimization in more conventional
architectures). The small size of instructions would eliminate I guess the
major problem of RISC as it is now (and that makes WISC attractive), code
density.
-- 
Piercarlo "Peter" Grandi           | ARPA: pcg%cs.aber.ac.uk@nsfnet-relay.ac.uk
Dept of CS, UCW Aberystwyth        | UUCP: ...!mcvax!ukc!aber-cs!pcg
Penglais, Aberystwyth SY23 3BZ, UK | INET: pcg@cs.aber.ac.uk