Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!b-tech!zeeff
From: zeeff@b-tech.ann-arbor.mi.us (Jon Zeeff)
Newsgroups: comp.arch
Subject: Re: Bandwidth and RISC vs. CISCOM
Message-ID: <9322@b-tech.ann-arbor.mi.us>
Date: 7 May 89 19:17:52 GMT
References: <38853@bbn.COM> <423@bnr-fos.UUCP> <288@ctycal.UUCP> <1262@l.cc.purdue.edu> <231@celit.UUCP> <10544@cit-vax.Caltech.Edu> <102714@sun.Eng.Sun.COM> <17932@cup.portal.com>
Reply-To: zeeff@b-tech.ann-arbor.mi.us (Jon Zeeff)
Organization: Branch Technology Ann Arbor, MI
Lines: 21

I don't see that much difference between WISC and a RISC chip and it's 
cache.  In both cases, you are eliminating the external memory 
accesses necessary to execute some common code sequence.  On the WISC 
chip, you have to set it up explicitly and invoke it with an 
instruction.  On the RISC/cache machine, it's automatic and invoked by 
the address being reused (meaning that it's going to have to be a 
subroutine if the code sequence is to be used from many different 
places in your code).  

Perhaps we need (or does it already exist) some instructions to 
control caching.  Something like "I'm about to execute some code that 
I know will be executed alot - keep it in the cache longer than usual" 
and "don't waste cache space on this - I'm only doing it once".  



Disclaimer - I just use CPUs.

-- 
  Jon Zeeff			zeeff@b-tech.ann-arbor.mi.us
  Ann Arbor, MI			sharkey!b-tech!zeeff