Path: utzoo!mnetor!tmsoft!dptcdc!lethe!dave
From: dave@lethe.UUCP (Dave Collier-Brown)
Newsgroups: comp.arch
Subject: Re: unconventional architectures
Summary: memory protection on ciscs
Message-ID: <2479@lethe.UUCP>
Date: 7 May 89 17:24:16 GMT
References: <112@centaure.UUCP> <422@unicads.UUCP> <11579@cgl.ucsf.EDU> <89May6.165030edt.10782@ephemeral.ai.toronto.edu> <1989May6.234007.23517@utzoo.uucp>
Reply-To: dave@lethe.UUCP (Dave Collier-Brown)
Organization: Officially bimodal, news courtesy of Systems Software
Lines: 27


>In article <89May6.165030edt.10782@ephemeral.ai.toronto.edu> bradb@ai.toronto.edu (Brad Brown) writes:
| >... we looked at a lot of old machines that had all kinds
| >of really neat features that you just don't see any more.  My favorite
| >was the Buroughs 6600 (?) and it's segmentation scheme...
| >... a lot of access bugs could be detected
| >at runtime with no performance penalty...

In article <1989May6.234007.23517@utzoo.uucp> henry@utzoo.uucp (Henry Spencer) writes:
| Unless you count the performance penalties implicit in implementing the
| rather complex design.  One can debate the size of said penalties, but it
| isn't correct to say that the bug detection is free.

  Well, it doesn't seem to add any extra overhead to the memory address
computation on a Honeywell, but I can't say for sure if the time taken
is actually dominated by instruction decoding, etc. I'd guess "yes" on
the older series 66 line, and a rather strong "no" on the DPS-90
(NEC-designed) machines.
  Designing a CISC is hard, but sometimes one finds that "wasted" time can
be usefully filled up.  The risc people seem to have noticed this too (;-))

 --dave 
-- 
David Collier-Brown,  | {toronto area...}lethe!dave
72 Abitibi Ave.,      |  Joyce C-B:
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