Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cornell!uw-beaver!uw-june!kolding
From: kolding@june.cs.washington.edu (Eric Koldinger)
Newsgroups: comp.arch
Subject: Re: Message queues
Message-ID: <8149@june.cs.washington.edu>
Date: 8 May 89 18:41:31 GMT
References: <279@celit.UUCP> <5668@microsoft.UUCP>
Reply-To: kolding@uw-june.UUCP (Eric Koldinger)
Organization: U of Washington, Computer Science, Seattle
Lines: 12

In article <279@celit.UUCP> hutch@celerity.UUCP (Jim Hutchison) writes:
>Has anyone seen/heard of an architecture which aided kernel message passing by
>supplying hardware message queues for *fast* message queueing and dequeueing?

IBM S/38 and AS/400 use message passing quite a bit in the kernel for IPC.  I
don't know how much is in hardware or how *fast* it is though.

-- 
	_   /|				Eric Koldinger
	\`o_O'				University of Washington
  	  ( )     "Gag Ack Barf"	Department of Computer Science
       	   U				kolding@cs.washington.edu