Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!purdue!tut.cis.ohio-state.edu!ucbvax!agate!bionet!csd4.milw.wisc.edu!uxc!iuvax!watmath!cantuar!greg
From: greg@cantuar.UUCP (G. Ewing)
Newsgroups: comp.arch,can.talk
Subject: Re: Bandwidth and RISC vs. CISC
Message-ID: <1106@cantuar.UUCP>
Date: 9 May 89 00:24:34 GMT
References: <38853@bbn.COM> <423@bnr-fos.UUCP> <288@ctycal.UUCP> <1262@l.cc.purdue.edu> <231@celit.UUCP> <10544@cit-vax.Caltech.Edu>
Reply-To: greg@cantuar.UUCP (G. Ewing)
Organization: University of Canterbury, Christchurch, New Zealand
Lines: 16

Yair Zadik (yair@tybalt.caltech.edu.UUCP) writes:
>A couple of years ago there was an article in Byte about a proposed design
>which they called WISC for Writeable Instruction Set Computer.  

Well, maybe the performance improvement would be debatable, but what
the heck - I think it would be fun!

In fact, I'd like to go further and make the processor sort of a
big writeable PAL! Rearrange the hardware according to the task
at hand. A WHISC (Writeable Hardware Interconnection Scheme Computer)?

Greg Ewing, Computer Science Dept, Canterbury Univ., Christchurch, New Zealand
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