Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!hc!lll-winken!uunet!mcvax!ukc!acorn!sfurber
From: SFurber@acorn.co.uk
Newsgroups: comp.arch
Subject: Semaphores
Message-ID: <759@acorn.co.uk>
Date: 9 May 89 09:36:04 GMT
Sender: sfurber@acorn.co.uk
Lines: 17





aglew@mcdurb.Urbana.Gould.COM writes:

>    Apparently the ARM does something similar, only checking for interrupts 
> at branches.

This is not correct. ARM checks for interrupts at the end of each and every
instruction. The store multiple register instruction allows a warped sort of
semaphore instruction to be built, and the new ARM3 (VL86C020) has an
uninterruptable memory to register SWAP instruction for just this purpose.


Steve Furber   sfurber@acorn.uucp
   Acorn Computers Ltd, England.