Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!unmvax!polyslo!ttwang
From: ttwang@polyslo.CalPoly.EDU (Thomas Wang)
Newsgroups: comp.arch
Subject: Re: Message queues
Message-ID: <11206@polyslo.CalPoly.EDU>
Date: 9 May 89 18:34:27 GMT
References: <279@celit.UUCP> <2277@cream-of-wheat.ai.mit.edu>
Reply-To: ttwang@polyslo.CalPoly.EDU (Thomas Wang)
Distribution: usa
Organization: Cal Poly State University -- San Luis Obispo
Lines: 13

In article <2277@cream-of-wheat.ai.mit.edu> lethin@cream-of-wheat.ai.mit.edu.WISC.EDU (Richard A. Lethin) writes:
>In article <279@celit.UUCP> hutch@celerity.UUCP (Jim Hutchison) writes:
>>Has anyone seen/heard of an architecture which aided kernel message passing by
>>supplying hardware message queues for *fast* message queueing and dequeueing?
>>/*    Jim Hutchison   		{dcdwest,ucbvax}!ucsd!celerity!hutch  */

Try H. Kanakia and D.R. Cheriton.  The VMP network adapter board NAB: High-
performance network communication for multiprocessors.  In SIGCOMM 88,
ACM SIGCOMM, Aug 1988

 -Thomas Wang (Anime drinking game - toast when you hear "Ayukawa!!!")

                                                     ttwang@polyslo.calpoly.edu