Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ulowell!m2c!wpi!jhallen
From: jhallen@wpi.wpi.edu (Joseph H Allen)
Newsgroups: comp.arch
Subject: Re: Semaphores
Message-ID: <2254@wpi.wpi.edu>
Date: 9 May 89 18:52:45 GMT
References: <759@acorn.co.uk>
Reply-To: jhallen@wpi.wpi.edu (Joseph H Allen)
Organization: Worcester Polytechnic Institute, Worcester, MA. USA
Lines: 39

In article <759@acorn.co.uk> SFurber@acorn.co.uk writes:

>This is not correct. ARM checks for interrupts at the end of each and every
>instruction. The store multiple register instruction allows a warped sort of
>semaphore instruction to be built, and the new ARM3 (VL86C020) has an
>uninterruptable memory to register SWAP instruction for just this purpose.

>Steve Furber   sfurber@acorn.uucp
>   Acorn Computers Ltd, England.

Speaking of warped semaphores, a nifty test-and-set instruction can be made on
machines (like 6809 where I originally used it) which have rotate memory:

Lock a resource:

wait:	ror	lock
	bcc	wait

Release a locked resource:

	inc	lock

This will even work in multiple-CPU situations as long as bus ownership
doesn't change in read-modify-write instructions 

(yes, I did write a multi-tasking OS on an 8-bit processor- interrupts caused
a task switch)
- - - - -

On a different note, how difficult is offset optomizations for machines (like
the ARM and most other RISC processors, I think) with offsets which are
smaller than the address space?

With the ARM, I notice that the lower 2 address bits are output.  Could these
be used to interrupt the processor for handling misaligned words? 

(yes, I did just get ARM chip info and I'm thinking of doing something neat
with this $45 dollor 32 bit chip- I also see that VLSI is planning to make
20Mhz and 32Mhz versions...  a 32Mhz version would faster than SPARC...)