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From: myavuzer@sutcase.case.syr.edu ( Mehmet Yavuzer)
Newsgroups: comp.lsi.cad
Subject: Prolog Algorithm
Message-ID: <1497@cmx.npac.syr.edu>
Date: 3 May 89 18:11:09 GMT
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Reply-To: myavuzer@sutcase.case.syr.edu ( Mehmet Yavuzer)
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Organization: CASE Center, Syracuse University
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I  am looking for a good Prolog algorithm for placement of
logic gates in vertical order where the objective is to
minimize number of wire intersections between adjacent levels
of gates.
This algorithm is intended to be used with a schematic layout
generator for networks of logic gates.