Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!iuvax!rutgers!mcnc!ecsvax!dukeac!rsb
From: rsb@dukeac.UUCP (R. Scott Bartlett)
Newsgroups: comp.sys.amiga.tech
Subject: Re: Need advice on hardware projects
Keywords: Refresh times
Message-ID: <1376@dukeac.UUCP>
Date: 28 Apr 89 04:35:10 GMT
References: <6678@cbmvax.UUCP>
Reply-To: rsb@dukeac.UUCP (R. Scott Bartlett)
Organization: Center for Demographic Studies, Duke University, Durham, NC
Lines: 42

In article <6678@cbmvax.UUCP> daveh@cbmvax.UUCP (Dave Haynie) writes:
>
>Absolutely true.  While you have more concerns about noise at those speeds,
>the main problem is the handling of refresh.  With a simple, normal speed
>SOTS memory card for the A1000, it's possible to interleave memory access
>with refresh, much as the CHIP memory works, and still run full speed with
>cheap (150ns) memories.  Once you even get to 14.3MHz on a 68020, even 100ns
>parts aren't fast enough on their own to give you no wait state operation,
>and they way you handle refresh can slow this down even more.  Refresh is
>basically another arbitration problem -- the 68020 wants the memory bus most
>of the time, but you need to supply a refresh to keep things going or you're
>in big trouble.  Thing is, you never know when the 68020 will be using the

Okay, I've been considering building a memory board for my A1000 for a while
now, but there is one thing that I have been unable to find out from people
that i have asked and the (somewhat dated) data books i have.  How often do
you need to refresh each individual column? (or is it a row?  sorry but it has
been a while since i have messed w/ this)  Do you need to wait for the full
time that a normal memory cycle would take (assuming CAS is already set up)?
Or can you strobe RAS (w/ the address set up already) and go on?  If so, how
long do you have to wait before you can either do a normal memory access or
another refresh?

About a year ago i calclated how often i would have to do a refresh based upon
my understanding of the timing information, and it turned out that the
processor would almost never be able to access the memory because it was
constantly being refreshed. (these were 256kDRAMS i was designing w/)  I
figured out that i was doing something really wrong, and i was misinterpreting
something seriously.  What gives?  Exactly how often does an individual cell
need to be refreshed before the charge leaks away?

			Thanks,

						rsb

--> can't wait for that '040 board running at 40Mhz!! Nudge, Nudge, Wink, Wink..

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