Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cornell!uw-beaver!mit-eddie!bloom-beacon!apple!oliveb!amiga!cbmvax!daveh
From: daveh@cbmvax.UUCP (Dave Haynie)
Newsgroups: comp.sys.amiga.tech
Subject: Re: Need advice on hardware projects
Message-ID: <6722@cbmvax.UUCP>
Date: 1 May 89 16:13:32 GMT
References: <1376@dukeac.UUCP>
Organization: Commodore Technology, West Chester, PA
Lines: 53

in article <1376@dukeac.UUCP>, rsb@dukeac.UUCP (R. Scott Bartlett) says:
> Keywords: Refresh times

> Okay, I've been considering building a memory board for my A1000 for a while
> now, but there is one thing that I have been unable to find out from people
> that i have asked and the (somewhat dated) data books i have.  How often do
> you need to refresh each individual column? (or is it a row?  sorry but it has
> been a while since i have messed w/ this)  

Refresh is done by row.  The exact refresh cycle will, of course, depend on the
chips you're dealing with.  The 256k density parts typically need a 256 row
refresh every 4ms, the 1 meg density parts typically need a 512 row refresh
every 8ms.  At least they made it easy this way, but this can vary by part type
and even a little by manufacturer.

> Do you need to wait for the full
> time that a normal memory cycle would take (assuming CAS is already set up)?
> Or can you strobe RAS (w/ the address set up already) and go on?  If so, how
> long do you have to wait before you can either do a normal memory access or
> another refresh?

The time is probably going to be driven by RAS, no matter how you go about
refreshing.  You'll typically have to keep RAS low for a whole Tras time, then
hold it high for a whole Trp time.  If you're providing the row address, you
have to worry about Tasr and Trah, if you're using the built-in refresh 
counters in a CAS before RAS cycle, you have a Tcsr to wait from CAS to RAS;
CAS going high won't be a gating item.  If you're setting up the so-called
hidden refresh cycle, where a normal cycle is immediately followed by a CAS
before RAS cycle, you're completely RAS driven; just keep CAS low 'till near
the end of the refresh cycle (there's some kind of CAS hold from RAS time to
consider, but it's no big deal).

> About a year ago i calclated how often i would have to do a refresh based upon
> my understanding of the timing information, and it turned out that the
> processor would almost never be able to access the memory because it was
> constantly being refreshed. 

Definitely something wrong there.  You didn't, perhaps, drop a power of 10^3
on the refresh timing, did you?  Refreshing every 4uS vs. every 4ms would 
certainly eat up most of the available time.  Also, on a slow memory board
(like a standard Amiga 16 bit memory system) there's enough time in a memory
cycle to interleave memory and refresh cycles.

> 						rsb

> --> can't wait for that '040 board running at 40Mhz!! Nudge, Nudge, Wink, Wink..

We'll have to see about that one.  I can safely say right now we're waiting on
Motorola for the chips...
-- 
Dave Haynie  "The 32 Bit Guy"     Commodore-Amiga  "The Crew That Never Rests"
   {uunet|pyramid|rutgers}!cbmvax!daveh      PLINK: D-DAVE H     BIX: hazy
              Amiga -- It's not just a job, it's an obsession