Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!ncar!noao!asuvax!mcdphx!teroach.UUCP!dbk
From: dbk@teroach.UUCP (Dave Kinzer)
Newsgroups: comp.sys.amiga.tech
Subject: Re: Re: Need advice on hardware projects
Summary: More advice
Keywords: Better memory through clean living
Message-ID: <10831@mcdphx.phx.mcd.mot.com>
Date: 2 May 89 05:22:31 GMT
References: <8905012101.AA25658@postgres.Berkeley.EDU>
Sender: listen@mcdphx.phx.mcd.mot.com
Reply-To: dbk@teroach.UUCP (Dave Kinzer)
Followup-To: comp.sys.amiga.tech
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Organization: Motorola Microcomputer Division, Tempe, Az.
Lines: 22


   Matt's good idea aside (being too difficult for SSI hackers), I've
always wondered why board designers don't use the lower address bits
(which cycle faster, typically) for the row address. Apart from the
considerations of page/nibble/column/etc mode, using the lowest 
address lines available will keep the DRAM capacitors more fully
charged, and thus less suceptable to changing state on an alpha hit.
Seems easy enough to do...


|    // GOATS - Gladly Offering All Their Support  Dave Kinzer (602)897-3085|
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In article <8905012101.AA25658@postgres.Berkeley.EDU> dillon@POSTGRES.BERKELEY.EDU (Matt Dillon) writes:
>	Refresh has always seemed so silly to me... nobody does the smart
>thing, which is to *monitor* the address bus and only supply refresh for
>the rows not accessed by the computer.  So, the more loaded your computer
>gets the fewer refresh cycles need to come in and steal time.
>	That isn't too difficult a function to add in a VLSI refresh 
>controller.
>					-Matt