Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!hplabs!hp-pcd!hplsla!tomb
From: tomb@hplsla.HP.COM (Tom Bruhns)
Newsgroups: comp.sys.amiga.tech
Subject: Re: Need advice on hardware projects
Message-ID: <170004@hplsla.HP.COM>
Date: 2 May 89 15:41:05 GMT
References: <9891@netnews.upenn.edu>
Organization: HP Lake Stevens, WA
Lines: 29

> 	Refresh has always seemed so silly to me... nobody does the smart
> thing, which is to *monitor* the address bus and only supply refresh for
> the rows not accessed by the computer.  So, the more loaded your computer
> gets the fewer refresh cycles need to come in and steal time.

I don't think it's fair to say _nobody_ does this -- but darned few do.
Of course another trick is to refresh through something that has to
happen to all rows anyway, like accessing for video pixel info (like I
believe the old Apples did -- and I guess the C64, too).  Then the
refresh comes essentially free.
> 
> 	That isn't too difficult a function to add in a VLSI refresh 
> controller.

Agreed!

Yet another very simple refresh technique:  if your processor will be
dead while awaiting the refresh completion anyway, and you can tolerate
doing the once-per-whatever-millisecond refresh all at once, simply let
the processor do it for you.  I worked this out on a 6502 some years
ago, letting a simple timer interrupt the processor (NMI, of course!)
to enter the refresh routine.  By very careful design you can get the
time down to the number of RAS cycles required for refresh, plus perhaps
a little overhead for the NMI/RTI.
> 
> 					-Matt
> ----------
Tom Bruhns
tomb%hplsla@hplabs.hp.com