Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!agate!shelby!apple!vsi1!wyse!mips!mash
From: mash@mips.COM (John Mashey)
Newsgroups: gnu.gcc
Subject: Re: Porting gcc to the new Sun SPARCstation 1 and SPARCstation 300 series
Message-ID: <19034@winchester.mips.COM>
Date: 8 May 89 18:45:15 GMT
References: <8905030323.AA27122@jato.Jpl.Nasa.Gov> <5441@cs.utexas.edu> <GRUNWALD.89May3093539@flute.cs.uiuc.edu>
Reply-To: mash@mips.COM (John Mashey)
Distribution: gnu
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 25

In article <GRUNWALD.89May3093539@flute.cs.uiuc.edu> grunwald@flute.cs.uiuc.edu writes:
>
>I've been curious about the talk of scheduling code mentioned here and
>elsewhere.
>
>Other than the possibility of schedules affecting register allocation,
>is there any reason to do schedules in the compiler? Would this be
>better supported by the assembler and/or an object-code-to-object-code
>scheduler?
>
>How is this done in the MIPS compiler?

1) Most of the code scheduling is done in the assembler.
2) The code generator and assembelr have been tuned to interact well.
For example, the classic "round-robin" use of temporaries is used, and
that seems to work pretty well with the current pipelines.
3) Code generators, and/or assembly code can turn code reordering on/off.
This is necessary, for example, for CPU diagnostics.  [The diags folks
went berserk the first time they tried to write a specific sequence,
and had it munged about!]
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
UUCP: 	{ames,decwrl,prls,pyramid}!mips!mash  OR  mash@mips.com
DDD:  	408-991-0253 or 408-720-1700, x253
USPS: 	MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086