Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cornell!uw-beaver!rice!titan!phil
From: phil@titan.rice.edu (William LeFebvre)
Newsgroups: sci.space.shuttle
Subject: Re: Shuttle Computer Info?
Message-ID: <3238@kalliope.rice.edu>
Date: 9 May 89 16:05:01 GMT
References: <24055@agate.BERKELEY.EDU> <3227@kalliope.rice.edu>
Sender: usenet@rice.edu
Reply-To: phil@Rice.edu (William LeFebvre)
Organization: Rice University, Houston
Lines: 34

In article <3227@kalliope.rice.edu> phil@hypatia.rice.edu (William LeFebvre) writes:
>I'll tell you what I know about them off the top of my head:  there are
>five General Purpose Computers (GPC) on board.  The hardware in each GPC
>is identical:  it is an IBM AP-101/B computer.  

Well, that will teach me to write "off the top of my head"!  Let's see how
many mistakes we can find:

>Typical IBM segmented architecture,

No, not typical.  No base registers.  It is really more like "extended
addressing" or bank switching.  The data bus is only 16 bits wide.  There
are extra bits in the program status word that define which "bank" to
address.

>but memory is addressed on 16-byte boundaries

Of course I meant "16-BIT" boundaries.

>Each GPC has 212 half-words of iron-ferrite core (yes, iron-ferrite core)

Well, it is iron-ferrite core, but there's a few more of them than 212.  I
seemed to have dropped a "K".  But it isn't 212K anyway, so the whole
statement was wrong.

THIS IS REALLY CORRECT (honest):  there are 208K half-words, which is the
same as 212,996 half words (K=1024), which is the same as 416K bytes.

You'd think I'd learn......

			William LeFebvre
			Department of Computer Science
			Rice University
			<phil@Rice.edu>