Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cornell!uw-beaver!rice!titan!phil
From: phil@titan.rice.edu (William LeFebvre)
Newsgroups: sci.space.shuttle
Subject: Re: Shuttle Computer Info?
Message-ID: <3239@kalliope.rice.edu>
Date: 9 May 89 16:43:04 GMT
References: <24055@agate.BERKELEY.EDU> <3227@kalliope.rice.edu> <2645@ndsuvax.UUCP>
Sender: usenet@rice.edu
Reply-To: phil@Rice.edu (William LeFebvre)
Organization: Rice University, Houston
Lines: 42

In article <2645@ndsuvax.UUCP> ncoverby@ndsuvax.UUCP (Glen Overby) writes:
>On another subject; I recall reading that the Shuttle's computers were so
>stuffed that to add something, something else had to be removed.  With a
>16MB address space, it would seem that more memory could be added and this
>could be avoided.

Where do you get 16MB address space from?  And even if the computer can
address that much, the address bus can still be a limiting factor.

Here's some more nitty gritty (are you sure you really want to know all
this?).  A GPC really consists of two boxes.  Those of you who watched the
on-board replacement procedure last Sunday saw the two separate boxes.  I
believe they replaced both of them.  One box is the CPU and the other box
is the IOP, or Input/Output Processor.  In the CPU there are 10 banks of
16K halfwords each, for a total of 160K halfwords.  But there's also some
memory in the IOP:  6 banks of 8K each, totalling 48K.  48+160 gives 208.
In the CPU, the address bus is only 16 bits wide.  The rest of memory is
addressed with "extended addressing" via extra bits in the PSW.  But the
bus between the IOP and the CPU that is used for DMA is only 18 bits plus
a parity bit, and it must specify the entire address.  Therein lies the
problem with upgrading the GPC.  They can easily go to 256K halfwords, but
that doesn't really give them much more memory.  If they go beyond 256K,
then the IOP cannot address the additional memory (if they put the memory
in the IOP box, then the CPU couldn't address it).  This problem is not
insurmountable, but it would require a much more clever compiler to put
all the right data in the right places.  And that would result in some
serious rearranging of the resulting assembly code.  And that would
require serious testing and recertification.

They want to go to 512K halfwords, which is the most the CPU can currently
address.  The PSW contains three extra bits for data fetches and three
extra bits for program fetches, so the limit is 2^19, or 512K.  Anything
higher would require serious redesign of the hardware.  If they want the
IOP to address anything higher than 256K, that would also require a
serious redesign.

Fun, huh?

			William LeFebvre
			Department of Computer Science
			Rice University
			<phil@Rice.edu>