Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!bbn!bbn.com!slackey
From: slackey@bbn.com (Stan Lackey)
Newsgroups: comp.arch
Subject: Re: Register usage [was Re: 80486 vs. 68040 code size]
Message-ID: <39803@bbn.COM>
Date: 11 May 89 13:41:05 GMT
References: <921@aber-cs.UUCP>
Sender: news@bbn.COM
Reply-To: slackey@BBN.COM (Stan Lackey)
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Organization: Bolt Beranek and Newman Inc., Cambridge MA
Lines: 22

In article <921@aber-cs.UUCP> pcg@cs.aber.ac.uk (Piercarlo Grandi) writes:
>In article <25546@amdcad.AMD.COM> tim@amd.com (Tim Olson) writes:
>    |     	Highly optimizing compilers have long been able to make very
>    |     	good use of more than four registers.
>    A static analysis of 495 functions shows that an average of 6.6 global
>    registers and an average of 7.0 local registers are used per function,
>Too bad that these figures don't mean anything, except that your compiler
>can 'make use of more than four registers'. The 'very good' after 'make' is
>not proved at all. To prove that you need to generate code assuming that you
>have say 1 to 16 register available, and then show that as the number of
>register increases, program speed/code size improves significantly.

A static analysis of registers-used can be very misleading.  The way
the Alliant compiler assigned registers was by cycling through all
those available.  This was because the machine was designed with a
scalar pipeline, and the allocator was trying to give the peepholer
the best chance at scheduling.  With this algorithm, the number of
registers used is "all of them".  To derive the number NEEDED requires
lots more work, and is certain to be not ony application dependent,
but likely even more dependent upon the writing style of the software
engineer.
-Stan