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From: tim@crackle.amd.com (Tim Olson)
Newsgroups: comp.arch
Subject: Re: Register usage [was Re: 80486 vs. 68040 code size]
Message-ID: <25589@amdcad.AMD.COM>
Date: 11 May 89 15:50:33 GMT
References: <921@aber-cs.UUCP> <39803@bbn.COM>
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Reply-To: tim@amd.com (Tim Olson)
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Organization: Advanced Micro Devices, Inc. Sunnyvale CA
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In article <39803@bbn.COM> slackey@BBN.COM (Stan Lackey) writes:
| A static analysis of registers-used can be very misleading. The way
| the Alliant compiler assigned registers was by cycling through all
| those available.  This was because the machine was designed with a
| scalar pipeline, and the allocator was trying to give the peepholer
| the best chance at scheduling.  With this algorithm, the number of
| registers used is "all of them".  To derive the number NEEDED requires
| lots more work, and is certain to be not ony application dependent,
| but likely even more dependent upon the writing style of the software
| engineer.

Agreed.  I just posted the static analysis because it was all I had time
for.  However, the compiler that was used does attempt to minimize
register usage through coloring, and does not use the cycling technique
you mention.



	-- Tim Olson
	Advanced Micro Devices
	(tim@amd.com)