Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!unmvax!polyslo!cquenel
From: cquenel@polyslo.CalPoly.EDU (18 more school days)
Newsgroups: comp.arch
Subject: Re: Register usage
Message-ID: <11293@polyslo.CalPoly.EDU>
Date: 11 May 89 19:32:47 GMT
References: <8905110956.AA12655@decwrl.dec.com>
Reply-To: cquenel@polyslo.CalPoly.EDU (18 more school days)
Organization: Blue Blaze Irregulars
Lines: 21

In 9851 neideck@nestvx.dec.com (Burkhard Neidecker-Lutz) writes:
	(a very informative and interesting summary of
	 a paper on register allocation)

>The compiler used was for the not-so-widely-known DECWRL Titan RISC machine,
>a ECL RISC with 64 non-windowed registers and a single cylce load.
                                                 ^^^^^^^^^^^^^^^^^

	This could have something to do with the degree of
	speed-up by removing these loads.  I don't think
	that they get very much bigger, but on RISC machines
	with a 1 or 2 cycle delay on a load from memory,
	the difference could be more significant.
	(And don't forget those nasty caches misses, that
	could be avoided once in a while).
	
-- 
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\. ./  | Chris (The Lab Rat) Quenelle      cquenel@polyslo.calpoly.edu |  \. ./
 \ /   |  You can keep my things, they've come to take me home -- PG   |   \ / 
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