Path: utzoo!attcan!uunet!cs.utexas.edu!tut.cis.ohio-state.edu!purdue!decwrl!nestvx.dec.com!neideck
From: neideck@nestvx.dec.com (Burkhard Neidecker-Lutz)
Newsgroups: comp.arch
Subject: Re: Register Scoreboarding
Message-ID: <8905120628.AA08299@decwrl.dec.com>
Date: 12 May 89 06:28:04 GMT
Organization: Digital Equipment Corporation
Lines: 20

In article 10198 henry@utzoo.uucp (Henry Spencer) writes:
 
>>Clamping the whole CPU on cache miss isn't a technique that can survive
>>into the 1990s.  I'm very curious to see what the non-scoreboard folks
>>will do.
>
>Probably pretty much what they do now:  let access and execution proceed
>in parallel, assuming the data isn't needed right away.
 
Ok, now I'm curious. What DOES a R[23]000, an AMD29000 or Sparc really do
if there's a data cache miss on a load but there are several instructions
behind it which aren't interested in the result. I guess machines with
a common I/D cache can't do anything as the cache will be busy getting the
missed data, so Sparc (current implementations) seems out (except for the
floating point coprocessor queue). I also know that at least the multiply
and divide units in R[23]000 will continue to work, but what about other
independent instructions past the load delay slot ?
 
	Burkhard Neidecker-Lutz, Digital CEC Karlsruhe, Project NESTOR
	neideck@nestvx.dec.com