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From: tim@crackle.amd.com (Tim Olson)
Newsgroups: comp.arch
Subject: Re: Register Scoreboarding
Message-ID: <25610@amdcad.AMD.COM>
Date: 12 May 89 15:41:54 GMT
References: <8905120628.AA08299@decwrl.dec.com>
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Reply-To: tim@amd.com (Tim Olson)
Organization: Advanced Micro Devices, Inc. Sunnyvale CA
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In article <8905120628.AA08299@decwrl.dec.com> neideck@nestvx.dec.com (Burkhard Neidecker-Lutz) writes:
| Ok, now I'm curious. What DOES a R[23]000, an AMD29000 or Sparc really do
| if there's a data cache miss on a load but there are several instructions
| behind it which aren't interested in the result. I guess machines with
| a common I/D cache can't do anything as the cache will be busy getting the
| missed data, so Sparc (current implementations) seems out (except for the
| floating point coprocessor queue). I also know that at least the multiply
| and divide units in R[23]000 will continue to work, but what about other
| independent instructions past the load delay slot ?

Since loads are fully interlocked on the Am29000, the processor will
continue to execute instructions until

	1) The results of the missed load are required
	2) The channel is required for another load or store




	-- Tim Olson
	Advanced Micro Devices
	(tim@amd.com)