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From: slackey@bbn.com (Stan Lackey)
Newsgroups: comp.arch
Subject: Re: 80486 vs. 68040 code size [really: how many regs]
Message-ID: <39887@bbn.COM>
Date: 12 May 89 17:42:54 GMT
References: <927@aber-cs.UUCP> <8082@killer.Dallas.TX.US>
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Reply-To: slackey@BBN.COM (Stan Lackey)
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In article <8082@killer.Dallas.TX.US> elg@killer.Dallas.TX.US (Eric Green) writes:
>in article <927@aber-cs.UUCP>, pcg@aber-cs.UUCP (Piercarlo Grandi) says:
>> used little. In a reg-mem architecture little use variables in memory do not
>> carry costs as high when you use them.
>
>Foo. If you use the variable three times, you've saved 4 memory
>fetches (2 addresses, 2 data) as vs. keeping it in a register. No matter
>what kind of machine you're using.

Don't confuse old microprocessors (the discussion context was 68000)
with real computers.  Yes I agree the 68000 serially did its memory
accesses as it needed them.  Many current current CISC's (1) have
instruction caches to supply the addresses in zero time and (2)
pipeline the memory data fetches in an earlier stage than the
execution.

As an example, on the Alliant, the instruction:

	ADDF <ea>, fp0

(1 cycle) takes the same amout of time as

	ADDF fp1, fp0

for displacement (16 and 32-bit), absolute, and auto-inc and -dec
addressing modes.  Two cycles if the memory data in unaligned.

Not to claim you don't need as many registers; pipelining actually does
make you want more, so you can take advantage of fetch-ahead and
store-behind.  Which uses lots or registers.
-Stan