Path: utzoo!attcan!uunet!cs.utexas.edu!tut.cis.ohio-state.edu!mailrus!csd4.milw.wisc.edu!leah!bingvaxu!sunybcs!boulder!unicads!les
From: les@unicads.UUCP (Les Milash)
Newsgroups: comp.arch
Subject: Re: Register usage [was Re: 80486 vs. 68040 code size]
Message-ID: <436@unicads.UUCP>
Date: 12 May 89 18:01:28 GMT
References: <921@aber-cs.UUCP> <1989May11.210653.2125@utzoo.uucp> <25602@amdcad.AMD.COM>
Reply-To: les@unicads.UUCP (Les Milash)
Organization: Unicad  Boulder, CO
Lines: 12

In article <25602@amdcad.AMD.COM> rpw3@amdcad.UUCP (Rob Warnock) writes:
>[..] Since with the Am29000, "spilling"
>a few regs to memory to make room for a new subroutine context usually
>does not cause a matching "fill" when the routine returns [those 128 local
>regs give you a *lot* of hysteresis], the interesting "knee of the curve"
>is in the tradeoff between cache spill/fill traffic and register cache size.
>That is, how much incremental spill/fill traffic do you save (thus incremental
>bus bandwidth saved and thus performance gained) for each additional register
>you put in the stack cache?

relatedly i had to admire sun installing compiler tricks to turn tail-
recursive C into iterative C.