Path: utzoo!attcan!uunet!cs.utexas.edu!sun-barr!ames!elroy!ucla-cs!marc
From: marc@oahu.cs.ucla.edu (Marc Tremblay)
Newsgroups: comp.arch
Subject: Re: Register Scoreboarding
Message-ID: <23884@shemp.CS.UCLA.EDU>
Date: 12 May 89 18:29:28 GMT
References: <24821@lll-winken.LLNL.GOV> <GRUNWALD.89May9113443@flute.cs.uiuc.edu> <3288@orca.WV.TEK.COM> <19463@winchester.mips.COM>
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Reply-To: marc@cs.ucla.edu (Marc Tremblay)
Organization: UCLA Computer Science Department
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In article <19463@winchester.mips.COM> mash@mips.COM (John Mashey) writes:
>	b) Load-misses (R3000s use write-thru caches, so there aren't really
>		store misses).
Since the R3000 uses write-thru caches and 
since the depth of the write buffer is 4, 
I assume that "stores" stall the processor only when more 
than 4 consecutive writes occur or whenever the buffer overflows. 
Saving the register file on a context switch could certainly
generate stalls if it is done sequentially (i.e without interleaving
register stores with non-store intructions).
From your comment I suppose that those situations do not occur very often?

					Marc Tremblay
					marc@CS.UCLA.EDU
					Computer Science Department, UCLA