Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!decwrl!nsc!voder!berlioz!nelson
From: nelson@berlioz (Ted Nelson)
Newsgroups: comp.arch
Subject: Re: Register usage [was Re: 80486 vs. 68040 code size]
Message-ID: <213@berlioz.nsc.com>
Date: 12 May 89 16:39:03 GMT
References: <921@aber-cs.UUCP> <18235@cup.portal.com>
Reply-To: nelson@berlioz.UUCP (Ted Nelson)
Distribution: usa
Organization: National Semiconductor, Santa Clara
Lines: 35

In article <18235@cup.portal.com> bcase@cup.portal.com (Brian Case) writes:
>
>Well, it's old and CISCy stuff, but the paper:
>
>Chow and Hennessey, "Register Allocation by Priority-based Coloring,"
>Proc. SIGPLAN Symp. on Compiler Construction, SIGPLAN notices vol. 19,
>No. 6, June 1984.
>
>shows some performance numbers for a variable number of registers.  The
>architectures were to the PDP-10 and the 68000.  A max. of 9 registers
>was available.  The fastest performance was achieved when the max. number
>of regs. was used.
>

It should be noted that in that article the effects of a variable number of
  registers was only run on the PDP-10, and furthermore only on short/simple
  programs such as the Queens Problem, Quicksort, etc.

The overall results were:
  0 registers:  1.0  (basis of comparison)
  2 registers:  0.88
  4 registers:  0.84
  6 registers:  0.75
  9 registers:  0.73

For most of the runs, the difference between 6 and 9 registers were minimal
  (0.01 or less), but differences > 0.01 showed up only in Quicksort, Fast
  Fourier Transform, Sieve, and inverse of a matrix.

It's an article worth reading.  If you're really looking for a wealth of
  data (applicable to CISC as well), peek at "Stategies for Managing the
  Register File in RISC" by Tamir and Sequin (IEEE Transactions on Comp,
  Vol C-32, # 11, November 1983, p. 977).

-- Ted.