Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!purdue!haven!adm!cmcl2!lanl!hc!lll-winken!vette!brooks
From: brooks@vette.llnl.gov (Eugene Brooks)
Newsgroups: comp.arch
Subject: Re: Register usage
Message-ID: <25219@lll-winken.LLNL.GOV>
Date: 14 May 89 19:50:46 GMT
References: <259@mindlink.UUCP>
Sender: usenet@lll-winken.LLNL.GOV
Reply-To: brooks@maddog.llnl.gov (Eugene Brooks)
Organization: Lawrence Livermore National Laboratory
Lines: 17

In article <259@mindlink.UUCP> a464@mindlink.UUCP (Bruce Dawson) writes:
>
>     One thing that needs to be kept in mind when talking about the advantages
>of huge numbers of registers is that some of the advantages of registers go
>away when you have a lot (when have you a lot availabel simultaneously I should
>say).  In the extreme case of the computer someone mentioned that had 256
>registers, a register-register operation would use up sixteen bits just to
>specify the two registers involved.  Contrast that with the six bits required
>if you only have eight registers.  Given the finite memory speeds that we have
Actually, if you have three register operation codes, you chew up 24 bits for
the register fields.  Add, say, an 8 bit operation code and you have 32 bits
for each basic computation instruction.  This is what we had for the instruction
set of the Cerberus multiprocessor simulator.  The instructions which need a
static offset for addressing are even wider, another 32 bits.  With the huge
size of code caches these days I don't see a problem here.

brooks@maddog.llnl.gov, brooks@maddog.uucp