Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!rutgers!apple!versatc!mips!mash
From: mash@mips.COM (John Mashey)
Newsgroups: comp.arch
Subject: Multiple Insstruction Issue & Low-Level Parallelism
Keywords: pipelines
Message-ID: <19755@winchester.mips.COM>
Date: 15 May 89 22:56:25 GMT
Lines: 21

There have been a number of discussions on such issues of late.
Here are a few useful papers, both from ASPLOS III (ACM SIGPLAN Notices,
May 1989):

Norm Jouppi & David Wall, "Availabel Instruction-Level Parallelism
for Superscalar and Superpipelined Machines", 272-282.

Michael Smith, Mike Johnson, Mark Horowitz, "Limits on Multiple
Instruction Issue", 290-302.

These: 
	are clearly written, with enough introductory material to
		to be accessible.
	are very relevant to topics upon which leading-edge RISC micro
		folks are working frenziedly.
	have DATA.
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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