Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!apple!oliveb!sun!chiba!khb
From: khb%chiba@Sun.COM (Keith Bierman - SPD Languages Marketing -- MTS)
Newsgroups: comp.arch
Subject: Re: Register Scoreboarding
Message-ID: <104998@sun.Eng.Sun.COM>
Date: 16 May 89 04:22:03 GMT
References: <8905120628.AA08299@decwrl.dec.com>
Sender: news@sun.Eng.Sun.COM
Reply-To: khb@sun.UUCP (Keith Bierman - SPD Languages Marketing -- MTS)
Organization: Sun Microsystems, Mountain View
Lines: 21

In article <8905120628.AA08299@decwrl.dec.com> neideck@nestvx.dec.com (Burkhard Neidecker-Lutz) writes:
>In article 10198 henry@utzoo.uucp (Henry Spencer) writes:
> 
> 
>Ok, now I'm curious. What DOES a ... or Sparc really do
>if there's a data cache miss on a load but there are several
>instructions ..

A good instruction scheduler places the "don't cares" after the load
so the load miss is simply irrelevant.

I can't comment on how well the current production SPARC compilers do
at this; but the Cydra 5 compiler did quite well at the equivalent
(keeping the memory pipe busy). Since the Cydra 5 had a minimum read
latency of 17 cycles this indicates (to me at least :>) that keeping
the current SPARC's from stalling should be acheivable.

Keith H. Bierman      |*My thoughts are my own. Only my work belongs to Sun*
It's Not My Fault     |	Marketing Technical Specialist    ! kbierman@sun.com
I Voted for Bill &    |   Languages and Performance Tools. 
Opus  (* strange as it may seem, I do more engineering now     *)