Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!apple!bbn!usc!elroy!ucla-cs!loving
From: loving@lanai.cs.ucla.edu (Mike Loving)
Newsgroups: comp.arch
Subject: Re: Multiport Micro Memories (was: Register Scoreboarding)
Message-ID: <23947@shemp.CS.UCLA.EDU>
Date: 16 May 89 06:28:08 GMT
References: <25395@ames.arc.nasa.gov>
Sender: news@CS.UCLA.EDU
Reply-To: loving@cs.ucla.edu (Mike Loving)
Organization: UCLA Computer Science Department
Lines: 24

In article <25395@ames.arc.nasa.gov> lamaster@ames.arc.nasa.gov (Hugh LaMaster) writes:
>
>When is someone going to stop spending so much time on
>the "easy" :-)   part of building what used to be a supercomputer in VLSI (CPU
>speed), and start spending some time on the hard part - fast multiport
>interleaved memory.  I would like to see someone come up with a cheap fast
>multiport memory interconnect.  
>

There is currently some interesting and (in my opinion) promising work going
on (last I heard) at the University of California at Davis on totally optical
interconnect which should go a long ways towards alleviating the processor
memory bottleneck.  The basic scheme allows the transfer of the entire contents
of the memory chip(s) (any size chip ya wanna build) in one fell swoop.  While
there will probably be difficulties with this technology (and all the others
trying anything new), when and if it works out it will greatly change the face
of the memory bandwidth problem.  For more info on this you should probably
contact Norm Matloff (matloff@iris.ucdavis.edu).


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Mike Loving          loving@lanai.cs.ucla.edu
                     . . . {hplabs,ucbvax,uunet}!cs.ucla.edu!loving
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