Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ncar!tank!uxc!uxc.cso.uiuc.edu!mcdurb!aglew
From: aglew@mcdurb.Urbana.Gould.COM
Newsgroups: comp.arch
Subject: Re: Understanding variations in Dhrysto
Message-ID: <28200314@mcdurb>
Date: 16 May 89 21:34:00 GMT
References: <474@estevax.UUCP>
Lines: 23
Nf-ID: #R:estevax.UUCP:474:mcdurb:28200314:000:1079
Nf-From: mcdurb.Urbana.Gould.COM!aglew    May 16 16:34:00 1989


>>[Weicker]
>>If the fixed-length and word-alignment assumption can be used, a wide
>>bus that permits fast multi-word load instructions certainly does help;
>
>[Spencer]
>Beware that there are alignment restrictions here too:  you don't want
>a multi-word load to cross a page boundary unless you are sure the string
>crosses it too.  Accessing the next page may cause a trap.

What I usually assume when people talk about wide busses is strict alignment.
Ie. you can read bytes at any byte address,
16 bits on even addresses only,
32 bits on mod 4 addresses only,
64 bits on mod 8 addresses only, 
2^(N+3) bit quantities on mod 2^N boundaries only, etc.
In these circumstances (which are the easiest to build - your memory boards
do not need to shift data)  then "bus-aligned" multi-word ops can be guaranteed
never to cross a page boundary (unless the bus is wider than the page. Hmm...)
Using such bus-aligned multi-word ops is legitimate for strings.

Now, whether a multi-word access can use multiple bus transactions is 
another question, that can lead to page crossings.