Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ncar!tank!uxc!uxc.cso.uiuc.edu!mcdurb!aglew
From: aglew@mcdurb.Urbana.Gould.COM
Newsgroups: comp.arch
Subject: Re: Multiport Micro Memories (was:
Message-ID: <28200315@mcdurb>
Date: 16 May 89 21:48:00 GMT
References: <25395@ames.arc.nasa.gov>
Lines: 23
Nf-ID: #R:ames.arc.nasa.gov:25395:mcdurb:28200315:000:1210
Nf-From: mcdurb.Urbana.Gould.COM!aglew    May 16 16:48:00 1989


>That reminds me.  We have seen some postings recently to the effect that
>connection technology is going to allow chips with some really large numbers
>of inputs/outputs.  When is someone going to stop spending so much time on
>the "easy" :-)   part of building what used to be a supercomputer in VLSI (CPU
>speed), and start spending some time on the hard part - fast multiport
>interleaved memory.  I would like to see someone come up with a cheap fast
>multiport memory interconnect.  

Now you're talking!!!  Lots of pins give us multiple ports - now how do we
use them?

To begin with: we need to start moving the parallelism of interleaved memory 
systems *within* the memory chips.  We know how to make expensive multichip
memory systems run fast. Trouble is, chip count is very strongly related
to system cost, and everyone wants cheaper systems.

We need memory chips that can keep several memory transactions going within
the chip - that have fast and powerful logic to snarf the data on writes,
and drive the read data out to the bus really quickly when it surfaces.
The various burst modes (page mode, nibble mode) are great, but it's time
that memory handled independent transactions well too.
w