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From: dkirk@k.gp.cs.cmu.edu (Dave Kirk)
Newsgroups: comp.arch
Subject: When is a RISC not a RISC {was Scoreboarding HW is simple}
Keywords: complex addressing, floating point instr
Message-ID: <5004@pt.cs.cmu.edu>
Date: 16 May 89 21:29:38 GMT
References: <19433@obiwan.mips.COM>
Organization: Carnegie-Mellon University, CS/RI
Lines: 38

In article <19433@obiwan.mips.COM> mark@mips.COM (Mark G. Johnson) writes:
>
>(The mechanism described is that implemented in Intel's embedded-
>controller RISC cpu, the 960.  Note the nine.)
>-- 
> -- Mark Johnson	
> 	MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
>	...!decwrl!mips!mark	(408) 991-0208

It's becoming less clear when a RISC stops being a RISC.  Intel's 80960
has certain features which definitely make the tag of a RISC chip
somewhat questionable.  It's not that I think Mark's terminology is
incorrect (indeed I'm sure more people agree with the RISC label), I
just wonder what features have to be missing/present to consider a CPU
a CISC.  

The 80960MC has addressing modes such as "Register Indirect with
Index and Displacement, data types including integer, real, decimal,
bit and byte, and the instruction set includes microcoded/interruptible/
multicycle instructions.  While some of this is unique to the MC version,
the 80960 still includes all of the addressing modes and multicycle 
instructions (shifts, multiply, divide ...)

Which feature is key in establishing the 80960 as a RISC:
	- load/store architecture;
	- register windows;
	- "some" single cycle instructions;
	- manufacturer's marketing claim?

Which features are key in establishing the 80960 as a CISC:
	- complex addressing schemes (index, displacement, indirection ...);
	- complex data types (floating point, decimal...);
	- multicycle instructions (flt pt, shifts, multiply/divide ...)?
 	
It seems difficult to decide if the 80960xx is RISC or CISC.
Is it possible that the 80960 is RISC and the 80960MC is CISC?

Flames to kirk@maxwell.ece.cmu.edu
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