Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!shadooby!accuvax.nwu.edu!nucsrl!naim
From: naim@eecs.nwu.edu (Naim Abdullah)
Newsgroups: comp.arch
Subject: Q-M tunneling limitations on feature size ?
Message-ID: <3810043@eecs.nwu.edu>
Date: 17 May 89 00:33:54 GMT
Organization: Northwestern U, Evanston IL, USA
Lines: 17

Can anybody provide a ball park figure for a feature size that will cause
quantum mechanical tunneling effects to cause a chip to malfunction ?

In other words, what is the lower bound on the feature size imposed by
q-m tunneling ? How far away are we from it ?

Please excuse the naive question. I am sure you comp.arch people have beaten
this horse many times, but I am just a software person looking in.

Thank you.

		      Naim Abdullah
		      Dept. of EECS,
		      Northwestern University

		      Internet: naim@eecs.nwu.edu
		      Uucp: {oddjob, chinet, att}!nucsrl!naim