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From: mslater@cup.portal.com (Michael Z Slater)
Newsgroups: comp.arch
Subject: Re: microprocessor 2nd-level cache protocols for multiprocessin
Message-ID: <18451@cup.portal.com>
Date: 17 May 89 03:14:20 GMT
References: <5481@hubcap.clemson.edu>
Organization: The Portal System (TM)
Lines: 14

>Is there any developing consensus concerning second-level cache consistency
>protocols in multiprocessor environments for 486 and 68040?  E.g. are the
>manufacturers such as Intel, Motorola, etc. going to use something like
>MOESI in 2nd-level cache chips?  

Intel has said that they will be introducing a second-level cache controller
chip, but they have not given any details.  I expect it in early '90.  It 
seems reasonable that they will support something like MOESI, but only time 
will tell.  As for Motorola, they hardly admit anything about the 68040, much
less any second-level cache support.  I wouldn't hold my breath for second-level
support from Moto, since the never did produce any integrated external cache
support for the 68020 or 68030, which really could have used it.

Michael Slater, Microprocessor Report    mslater@cup.portal.com