Path: utzoo!attcan!uunet!lll-winken!xanth!ames!apple!sun-barr!texsun!pitstop!jwest
From: jwest@pitstop.West.Sun.COM (Jeremy West)
Newsgroups: comp.arch
Subject: Re: Criteria ... [really: are N designs better than 1?]
Message-ID: <674@pitstop.West.Sun.COM>
Date: 18 May 89 16:55:34 GMT
References: <2368@ogccse.ogc.edu> <1464@cfa.cfa.harvard.EDU> <141@dg.dg.com> <19088@winchester.mips.COM>
Organization: Sun Microsystems, Mt. View, CA
Lines: 34


I'm sorry that it has taken so long to respond to John's mega message,
(I don't get to read news often enough) but I wanted to make a few points.

A large number of comp.arch readers are interested in embedded
realtime and a large number of SPARC designs are  in this category.
For them an integer unit is all you need. I take the points about
availability of full chipsets at hign clock rates.

John's questions about clones exceeding Sun in SPARC production rates
were interesting, how long did it take for IBM to drop below 50%
of the PC market? What happened to the (uncloned) DEC Rainbow in the meantime?
(The above is not architecture but it is short - don's asbestos Y-fronts.. :-)

On architecture, my OPINION is that there are a lot of good design tems
around and that anyone who wants to build their own processor can
have a lot of implementation freedom while still being SPARC binary
compatible and getting the software base without having to
start from scratch.

On cost issues, John says:
> Both SPARC and MIPS
	need the same speed vanilla SRAMs at the same clock rate, I think,

I disagree and so do Cypress (who sell SRAMs to MIPS?) MIPS need much
faster SRAMS because of their two phase memory bus at a given clock
rate. We could try to compare the 25MHz 4/330 CPU to a 
MIPS based CPU board to settle this.

Adrian Cockcroft	disclaimer: these are personal opinions
Sun Cambridge UK TSE
sun!sunuk!acockcroft

(Borrowing Jerry West's account at Mountain View to get at USENET)